1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device in which a source region silicide layer is used to bias an underlying substrate or well.
2. Description of the Related Art
As semiconductor devices develop toward high integration, high performance, and low voltage operation, a low-resistance gate material is required to reduce the gate length of a transistor and a memory cell through the formation of fine patterns and to improve the device""s characteristics. The thickness of a gate insulating layer must in turn become smaller to increase a channel current in a transistor and a memory cell for low voltage operation. Furthermore, in order to prevent short channel effects caused by the decrease in the gate length of a transistor and to ensure a margin against punch-through, the junction depth of the source/drain regions should be reduced and the parasitic resistance, that is, the surface resistance and the contact resistance of the source/drain regions should be reduced.
Under these circumstances, studies have been conducted on a self-aligned silicide (salicide) process to reduce the resistivity of a gate and the sheet and contact resistance of source/drain regions. This self-aligned silicide process operates by forming a silicide layer on the surfaces of the gate and the source/drain regions. The salicide process refers to the selective formation of a silicide layer such as a titanium silicide (TiSiX) layer on a gate electrode and source/drain regions.
FIG. 1 is a vertical sectional view of an N-channel MOS (Metal Oxide Semiconductor) transistor fabricated by a conventional salicide process. As shown in FIG. 1, a gate insulating layer 112 is grown by performing a thermal oxidation on the surface of a silicon substrate 110 that has an active region on it, defined by a field oxide film (not shown). A conductive layer such as a polysilicon is then deposited for use as a gate, on the gate insulating layer 112 by CVD (Chemical Vapor Deposition). The polysilicon layer is then doped to be of an N-type by ion implantation and is then patterned into a gate 114 by photolithography.
Subsequently, Nxe2x88x92 active regions 116 are formed as lightly doped drain (LDD) regions on the surface of the substrate 110 at opposite sides of the gate 114 by ion-implanting an N-type dopant. In particular, phosphorous (P) may be used at a low dose (e.g., at a dose of 1xc3x971013-9xc3x971014 ions/cm2) with the gate 114 being used as an ion-implanting mask.
Spacers 118 are then formed on the sidewalls of the gate 114 by depositing an insulating layer on the resultant structure, including the Nxe2x88x92 active regions 116, and then etching back the insulating layer by anisotropical etching such as RIE (Reactive Ion Etching). Here, the insulating layer is formed of a silicidation blocking material, such as a nitride or an oxide. Then, N+ active regions 120 are formed as high-concentration source/drain regions on the surface of the substrate 110 at opposite sides of the spacers 118 by ion-implanting an N-type dopant. In particular, arsenic (As) may be used at a high dose (e.g., at or above a dose of 1xc3x971015 ions/cm2) with the spacers 118 and the gate 114 being used as an ion-implanting mask.
Afterwards, a silicide forming metal material, such as titanium (Ti) is deposited on the resultant structure, including the N+ active regions 120, and the titanium is subjected to rapid thermal annealing (RTA) or thermal treatment using a furnace so that silicidation takes place in an area where the titanium contacts silicon. As a result, a titanium silicide (TiSi2) layer is formed on the surfaces of the exposed Nxe2x88x92 and N+ active regions 116 and 120 and on the gate 114. Then, an unreacted titanium layer is selectively removed, using an etchant which does not damage the silicide layer 122, the silicon substrate 110, or the gate insulating layer 112.
A problem with the conventional method is incomplete silicidation on the surface of a narrow active region (see xe2x80x9cAxe2x80x9d of FIG. 1). This is believed to be caused by the impurity concentration in the silicon substrate 110. In other words, with the ion-implantation on the silicon substrate 110 at or above a dose of 1xc3x971015 ions/cm2, impurities contained in the silicon in excess of their solid solubility limit are segregated or piled up at the titanium/silicon interface, thereby blocking the diffusion of silicon. This phenomenon is observed to be more serious with arsenic than with phosphorous.
As a result, the diffusion of silicon is more difficult in the narrow region A of FIG. 1 between gates 114, than in the remainder of the device. This can lead to incomplete silicidation as compared to a wide region or an increased sheet resistance. For example, when the source region of a transistor, coupled to a common source terminal (Vss) of memory cells, is narrow, silicon of a substrate is not sufficiently diffused in the narrow region during the step of forming a titanium silicide layer. As a result, the sheet resistance from the source region to a Vss pattern may increase. In a worse case situation, no suicide layer may be formed at all, thereby reducing a voltage margin in a low-voltage operation area of a device.
As a separate issue, a general problem with CMOS circuits is their propensity to xe2x80x9clatch-upxe2x80x9d. Latch-up arises from the presence of complementary parasitic bipolar transistor structures, which result from fabrication of complementary MOS devices in a CMOS structure. Because they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like p-n-p-n diodes.
This is a phenomenon that establishes a very low-resistance path between the Vcc and Vss power lines, which in turn allows large currents to flow through the circuit. This can cause the circuit to malfunction or not function at all due to heat caused by high power dissipation. The latch-up phenomenon is triggered by a changing current incidental to the fluctuation of power supply voltage, a punch through current at a well boundary, etc. Such triggering currents may be and in practice are established in any one or more of a variety of ways, e.g., terminal overvoltage stress, transient displacement currents, ionizing radiation, or impact ionization by hot electrons.
FIG. 2 is a cross-sectional view of an SRAM cell comprising a CMOS device having a p-channel transistor 210 formed in an n-well 212 diffused into a p-type substrate 213, and an n-channel transistor 211 formed directly in the substrate 213. As shown in FIG. 2, two bipolar transistors 214 and 215 are parasitically formed in the SRAM cell.
When a trigger current is generated in the p-well 212, current flows through a resistance Rs, and the voltage drop across the resistance Rs turns on the bipolar transistor 214. When the bipolar transistor 214 turns on, a collector current thereof flows through a resistance Rw and a bias power supply Vcc. As a consequence, the base-emitter of the bipolar transistor 215 is biased in the forward direction, and the bipolar transistor 215 also turns on. When the bipolar transistor 215 turns on, the collector current thereof flows through the resistance Rs, further increasing the base potential of the bipolar transistor 214 which has already been turned on. Consequently, the collector current of the bipolar transistor 214 is again increased, further driving the bipolar transistor 215. As a result, the bipolar transistors 214 and 215 become completely turned on, and a large current flows from the bias power supply Vcc to the bias voltage Vss.
The bias voltages Vss to the p-well and Vcc to the n-well can be used to set the potentials of the p-well and n-well so as to suppress the latch-up phenomenon, i.e., to avoid the forward bias condition between the emitter and base electrodes of bipolar transistor 214. However, as shown in FIG. 3, in the conventional SRAM cell array, there are a plurality of circuit cells aligned and connected to each other. The bias voltage Vcc is supplied to the common n-well region in which the p-channel MOS transistors of the cells are strapped. Similarly, Vss is supplied to the common p-well region in which the n-channel MOS transistors of cells are formed. The conductive contact for providing the bias voltage Vcc (or Vss) is located at only one portion of the common n-well (or common p-well). The increased resistance at areas distant from the biasing contacts causes undesirable power supply and ground noise. In this state, the latch-up phenomenon can still occur.
Another problem encountered with the SRAM CMOS device is xe2x80x9csoft errorxe2x80x9d. If energetic particles from the environment (e.g. alpha-particles) should happen to strike a junction (e.g., a drain junction) surrounded by a depletion region, electrons and holes will be generated within the underlying body of the semiconductor material and will collect along the boundary of the depletion region, and the voltage across the junction will be reduced by the charge perturbation. If the charge perturbation is sufficiently large, the stored logic state may be reversed. This is commonly referred to as a xe2x80x9csoft errorxe2x80x9d since the error is not due to a hardware defect and since the cell will operate normally thereafter. Like latch up, soft errors are also increased by the unstable potential of a well stand-by operation at reduced voltages.
According to a first aspect of the present invention, a semiconductor device includes a substrate of a first conductive type; a well region of a second conductive type formed in the substrate, wherein the second conductive type is opposite the first conductive type; a first impurity region of the first conductive type extending to a first depth within the well region; a second impurity region of the first conductive type spaced from the first impurity region to define a channel region therebetween and extending to a second depth within the well region; a gate electrode located over the channel region; a silicide layer formed at a third depth within the first impurity region, wherein the third depth is less than the first depth, and wherein a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer. Preferably, the second depth is greater than the first depth.
According to another aspect of the present invention, a semiconductor device includes a substrate of a first conductive type; a well region of a second conductive type formed in the substrate, wherein the second conductive type is opposite the first conductive type; a first impurity region of the first conductive type extending to a first depth within the well region; a second impurity region of the first conductive type spaced from the first impurity region to define a channel region therebetween and extending to a second depth within the well region; a gate electrode located over the channel region; and a silicide layer formed within the first impurity region and including protrusions extending downwardly from a bottom surface thereof and across a boundary between the first impurity region and the well region. Again, the second depth is preferably greater than the first depth.
According to still another aspect of the present invention, a semiconductor device includes a substrate of a first conductive type; a well region of a second conductive type formed in the substrate, wherein the second conductive type is opposite the first conductive type; first and second voltage nodes; a first transistor comprising (a) a first impurity region of the first conductive type extending to a first depth within the well region, (b) a second impurity region of the first conductive type spaced from the first impurity region to define a channel region therebetween and extending to a second depth within the well region, (c) a gate electrode located over the channel region, and (d) a silicide layer connected to the first voltage node and formed at a third depth within the first impurity region, wherein the third depth is less than the first depth, and wherein a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer; and a second transistor comprising (a) a first impurity region of the second conductive type extending to a first depth within the substrate, (b) a second impurity region of the second conductive type spaced from the first impurity region to define a channel region therebetween and extending to a second depth within the substrate, (c) a gate electrode located over the channel region, and (d) a silicide layer connected to the second voltage node and formed at a third depth within the first impurity region, wherein the third depth is less than the first depth, and wherein a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the substrate is sufficient to electrically bias the substrate through the silicide layer.
According to yet another aspect of the present invention, a semiconductor device includes a substrate of a first conductive type; a well region of a second conductive type formed in the substrate, wherein the second conductive type is opposite the first conductive type; first and second voltage nodes; a first transistor comprising (a) a first impurity region of the first conductive type extending to a first depth within the well region, (b) a second impurity region of the first conductive type spaced from the first impurity region to define a channel region therebetween and extending to a second depth within the well region, (c) a gate electrode located over the channel region, and (d) a silicide layer connected to the first voltage node and formed within the first impurity region and including protrusions extending downwardly from the bottom surface thereof and across a boundary between the first impurity region and the well region; and a second transistor comprising (a) a first impurity region of the second conductive type extending to a first depth within the substrate, (b) a second impurity region of the second conductive type spaced from the first impurity region to define a channel region therebetween and extending to a second depth within the substrate, (c) a gate electrode located over the channel region, and (d) a suicide layer connected to the second voltage node and formed within the first impurity region and including protrusions extending downwardly from the bottom surface thereof and across a boundary between the first impurity region and the substrate.